The present invention relates to a manner of implementing complex non-symmetrical bit parallel data processing circuits in a plurality of integrated circuits. The advantages of employing custom designed integrated circuits for data processing applications is well known. These advantages include enhanced speed of operation, reduced final construction and assembly costs and increased reliability. It would be ideal if each desired data processing circuit could be integrated on to a single integrated circuit. However, there are many cases in which a complex data processing circuit cannot be placed all on a single integrated circuit because this data processing circuit involves too many signal input and output lines or is too complex as a whole for integration onto a single chip. However, many of the advantages of integration of a complex data processing circuit may be achieved by constructing this circuit of a small number of integrated circuits. Therefore, it is still advantageous to provide a complex data processing circuit in a small number of integrated circuits.
The prior art includes two techniques for construction of an integrated circuit set to embody complex logic functions which cannot be integrated onto a single chip. In the first technique, the complex data processing circuit is divided along functional lines. Then a number of different integrated circuits are construced in order to perform each of these differing functions. In the event that these functional elements are not standard integrated circuits, then a number of custom integrated circuit chips must be designed and manufactured in order to produce the data processing circuit. In many cases this technique is technically feasible. However, in other cases this scheme cannot be used because the interconnection required between these separate functions becomes too complex. A second technique employed to solve this problem involves division of the complex data processing circuit along bit boundaries. In such a case, each individual circuit may include a two-bit slice, a four-bit slice or other convenient number of bits. This solution is advantageous when each bit is identical, and therefore each of the bit slices are identical. However, in the case of a non-symmetrical data processing circuit, that is in the case when all bits do not include the same logic circuitry, this technique requires the construction of a number of differing custom integrated circuits. This technique does have the advantage that the interconnection between these integrated circuits is relatively straightforward.
Each of the techniques noted above have a substantial disadvantage. Each of these techniques require that a number of different custom integrated circuit designs be made. This requirement is disadvantageous because of the substantial cost involved in designing and tooling for manufacture of an integrated circuit. Each new custom integrated circuit requires a minimum of $300,000 to $500,000 regardless of the complexity of the integrated circuit design. Of course, a more complicated integrated circuit design would require a greater initial investment. In addition, a circuit which required fewer different types of custom integrated circuits would require greater numbers of each type. These greater numbers of each type contribute to enhanced yield and hence lower cost per integrated circuit. Therefore, it is highly advantageous from a cost standpoint in order to be able to minimize the number of custom integrated circuit designs required to implement the complex data processing circuit.